AD9516-3BCPZ-REEL7 IC CLOCK PLL/VCO 2GHZ 64LFCSP

Description

The AD9516-31 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an onchip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used. The AD9516-3 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements. FUNCTIONAL BLOCK DIAGRAM REFIN REF1 REF2 CLK LF SWITCHOVER AND MONITOR PLL DIVIDER AND MUXs CP VCO STATUS MONITOR LVPECL LVPECL LVPECL LVDS/CMOS LVDS/CMOS SERIAL CONTROL PORT AND DIGITAL LOGIC AD9516-3 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 DIV/Φ DIV/Φ DIV/Φ DIV/Φ DIV/Φ DIV/Φ DIV/Φ Δt Δt Δt Δt 06422-001 Figure 1. The AD9516-3 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz. Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024. The AD9516-3 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal). The AD9516-3 is specified for operation over the standard industrial range of −40°C to +85°C.